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8430252cg-45 www.icst.com/products/hiperclocks.html rev. b december 9, 2005 1 integrated circuit systems, inc. ICS8430252-45 f emto c locks ? c rystal - to -3.3v lvpecl f requency s ynthesizer preliminary g eneral d escription the ICS8430252-45 is a 2 output lvpecl and lvcmos/lvttl synthesizer optimized to gen- erate ethernet reference clock frequencies and is a member of the hiperclocks? family of high performance clock solutions from ics. using a 25mhz, 18pf parallel resonant crystal, the following fre- quencies can be generated: 156.25mhz lvpecl output and, 125mhz lvcmos output. the 8430252-45 uses ics? 3rd generation low phase noise vco technology and can achieve 1ps or lower typical rms phase jitter, easily meet- ing ethernet jitter requirements. the ICS8430252-45 is packaged in a small 16-pin tssop package. f eatures ? one differential 3.3v lvpecl output and one lvcmos/lvttl output ? crystal oscillator interface designed for a 25mhz, 18pf parallel resonant crystal ? a 25mhz crystal generates both an output frequency of 156.25mhz (lvpecl) and 125mhz (lvcmos) ? vco frequency: 625mhz ? rms phase jitter @ 156.25mhz (1.875mhz - 20mhz) using a 25mhz crystal: 0.39ps (typical) ? full 3.3v supply mode ? 0c to 70c ambient operating temperature ? industrial temperature available upon request ? available in both standard and lead-free rohs compliant packages hiperclocks? ic s b lock d iagram xtal_in xtal_out qa qb nqb p in a ssignment oe v ee qa v cco _ a nc nc v cca v cc 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 clk_en v ee qb nqb v cco _ b xtal_in xtal_out v ee ICS8430252-45 16-lead tssop 4.4mm x 5.0mm x 0.92mm package body g package top view osc phase detector vco 625mhz feedback divider 25 4 5 25mhz clk_en oe pullup pullup the preliminary information presented herein represents a product in prototyping or pre-production. the noted characteristics a re based on initial product characterization. integrated circuit systems, incorporated (ics) reserves the right to change any circuitry or specific ations without notice.
8430252cg-45 www.icst.com/products/hiperclocks.html rev. b december 9, 2005 2 integrated circuit systems, inc. ICS8430252-45 f emto c locks ? c rystal - to -3.3v lvpecl f requency s ynthesizer preliminary t able 1. p in d escriptions t able 2. p in c haracteristics t u p n it u p t u o e oa q 0z - i h 1e v i t c a t able 3a. oe s elect f unction t able t u p n is t u p t u o n e _ k l cb qb q n 0w o lh g i h 1e v i t c ae v i t c a t able 3b. clk_en s elect f unction t able l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p c d p e c n a t i c a p a c n o i t a p i s s i d r e w o pv c c v , a c c v , , a _ o c c v b _ o c c v 5 6 4 . 3 =0 1f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r e b m u ne m a ne p y tn o i t p i r c s e d 1e ot u p n ip u l l u p . s l e v e l e c a f r e t n i l t t v l / s o m c v l . n i p e l b a n e t u p t u o . e l b a t n o i t c n u f a 3 e l b a t e e s 5 1 , 9 , 2v e e r e w o p. n i p y l p p u s e v i t a g e n 3a qt u p t u o. t u p t u o k c o l c l t t v l / s o m c v l 4v a _ o c c r e w o p. t u p t u o a q r o f n i p y l p p u s t u p t u o 6 , 5c nd e s u n u. t c e n n o c o n 7v a c c r e w o p. n i p y l p p u s g o l a n a 8v c c r e w o p. n i p y l p p u s e r o c 1 1 , 0 1 , t u o _ l a t x n i _ l a t x t u p n i . t u p t u o e h t s i t u o _ l a t x , t u p n i e h t s i n i _ l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c 2 1v b _ o c c r e w o p. s t u p t u o b q n , b q r o f n i p y l p p u s t u p t u o 4 1 , 3 1b q , b q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . s t u p t u o k c o l c l a i t n e r e f f i d 6 1n e _ k l ct u p n ip u l l u p . s l e v e l e c a f r e t n i l t t v l / s o m c v l . n i p e l b a n e k c o l c . e l b a t n o i t c n u f b 3 e l b a t e e s
8430252cg-45 www.icst.com/products/hiperclocks.html rev. b december 9, 2005 3 integrated circuit systems, inc. ICS8430252-45 f emto c locks ? c rystal - to -3.3v lvpecl f requency s ynthesizer preliminary t able 4a. p ower s upply dc c haracteristics , v cc = v cca = v cco_a, v cco_b = 3.3v5%, t a = 0c to 70c t able 4b. lvcmos / lvttl dc c haracteristics , v cc = v cca = v cco_a = 3.3v5%, t a = 0c to 70c a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 89c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v c c 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n in e _ k l c , e ov c c v = n i v 5 6 4 . 3 =5 i l i t n e r r u c w o l t u p n in e _ k l c , e ov c c v , v 5 6 4 . 3 = n i v 0 =0 5 1 - v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 6 . 2v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 . 0v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t a _ o c c , n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . 2 / . " t i u c r i c t s e t d a o l t u p t u o v 3 . 3 " t able 4c. lvpecl dc c haracteristics , v cc = v cca = v cco_b = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov o c c 4 . 1 -v o c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov o c c 0 . 2 -v o c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t b _ o c c . v 2 - l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v v , a _ o c c v b _ o c c e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i e e t n e r r u c y l p p u s r e w o p 5 7a m i a c c t n e r r u c y l p p u s g o l a n a 8a m
8430252cg-45 www.icst.com/products/hiperclocks.html rev. b december 9, 2005 4 integrated circuit systems, inc. ICS8430252-45 f emto c locks ? c rystal - to -3.3v lvpecl f requency s ynthesizer preliminary t able 6. ac c haracteristics , v cc = v cca = v cco_a, v cco_b = 3.3v5%, ta = 0c to 70c t able 5. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 5 2z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 e c n a t i c a p a c t n u h s 7f p l e v e l e v i r d 1w m . l a t s y r c t n a n o s e r l e l l a r a p f p 8 1 n a g n i s u d e z i r e t c a r a h c : e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o e g n a r y c n e u q e r f t u p t u o 5 2 . 6 5 1z h m 5 2 1z h m t ) ? ( t i j r e t t i j e s a h p s m r 1 e t o n ; ) m o d n a r ( a q) z h m 0 2 - z h m 5 7 8 . 1 ( z h m 5 2 11 4 . 0s p b q n , b q) z h m 0 2 - z h m 5 7 8 . 1 ( z h m 5 2 . 6 5 19 3 . 0s p t r t / f t u p t u o e m i t l l a f / e s i r a q % 0 8 o t % 0 2 5 7 7s p b q n , b q0 9 3s p c d oe l c y c y t u d t u p t u o a q0 5% b q n , b q0 5% . s t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 1 e t o n
8430252cg-45 www.icst.com/products/hiperclocks.html rev. b december 9, 2005 5 integrated circuit systems, inc. ICS8430252-45 f emto c locks ? c rystal - to -3.3v lvpecl f requency s ynthesizer preliminary 156.25mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.39ps (typical) o ffset f requency (h z ) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1m 10m 100m phase noise result by adding 10gb ethernet filterto raw data raw phase noise data dbc hz n oise p ower t ypical p hase n oise at 156.25mh z 10gb ethernet filter ? ? ?
8430252cg-45 www.icst.com/products/hiperclocks.html rev. b december 9, 2005 6 integrated circuit systems, inc. ICS8430252-45 f emto c locks ? c rystal - to -3.3v lvpecl f requency s ynthesizer preliminary p arameter m easurement i nformation t pw t period t pw t period odc = x 100% qb rms p hase j itter 3.3v c ore /3.3v lvcmos o utput l oad ac t est c ircuit 3.3v c ore /3.3v lvpecl o utput l oad ac t est c ircuit scope qx nqx lvpecl 2v -1.3v0.165v lvcmos o utput d uty c ycle /p ulse w idth /p eriod clock outputs 20% 80% 80% 20% t r t f v sw i n g v cc , v cca , v cco_b v ee nqb lvpecl o utput r ise /f all t ime phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power scope qx lvcmos 1.65v5% -1.65v5% v cc , v cca , v cco_a v ee t period t pw t period odc = x 100% v cco_lvcmos 2 t pw qa clock outputs 20% 80% 80% 20% t r t f lvpecl o utput d uty c ycle /p ulse w idth /p eriod lvcmos o utput r ise /f all t ime
8430252cg-45 www.icst.com/products/hiperclocks.html rev. b december 9, 2005 7 integrated circuit systems, inc. ICS8430252-45 f emto c locks ? c rystal - to -3.3v lvpecl f requency s ynthesizer preliminary a pplication i nformation c rystal i nput i nterface the ICS8430252-45 has been characterized with 18pf parallel resonant crystals. the capacitor values shown in figure 2 below were determined using a 25mhz, 18pf figure 2. c rystal i npu t i nterface parallel resonant crystal and were chosen to minimize the ppm error. p ower s upply f iltering t echniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ICS8430252-45 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , v cca , and v cco_x should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v cca pin. f igure 1. p ower s upply f iltering 10 v cca 10 f .01 f 3.3v .01 f v cc c1 22p x1 18pf parallel crystal c2 22p xtal_out xtal_in
8430252cg-45 www.icst.com/products/hiperclocks.html rev. b december 9, 2005 8 integrated circuit systems, inc. ICS8430252-45 f emto c locks ? c rystal - to -3.3v lvpecl f requency s ynthesizer preliminary t ermination for 3.3v lvpecl o utput v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin the clock layout topology shown below is a typical termi- nation for lvpecl outputs. the two different layouts men- tioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, ter- minating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are f igure 3b. lvpecl o utput t ermination f igure 3a. lvpecl o utput t ermination designed to drive 50 transmission lines. matched imped- ance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed cir- cuit and clock component process variations. i nputs : s elect p ins : all select pins have internal pull-ups and pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvcmos o utput : all unused lvcmos output can be left floating. we recommend that there is no trace attached. lvpecl o utput all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
8430252cg-45 www.icst.com/products/hiperclocks.html rev. b december 9, 2005 9 integrated circuit systems, inc. ICS8430252-45 f emto c locks ? c rystal - to -3.3v lvpecl f requency s ynthesizer preliminary p ower c onsiderations this section provides information on power dissipation and junction temperature for the ICS8430252-45. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS8430252-45 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 75ma = 259.88mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 2 * 30mw = 90mw total power _max (3.465v, with all outputs switching) = 259.9mw + 60mw = 319.9mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8c/w per table 7 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.320w * 81.8c/w = 96.2c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 7. t hermal r esistance ja for 16- pin tssop, f orced c onvection ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 137.1c/w 118.2c/w 106.8c/w multi-layer pcb, jedec standard test boards 89. 0c/w 81.8c/w 78.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
8430252cg-45 www.icst.com/products/hiperclocks.html rev. b december 9, 2005 10 integrated circuit systems, inc. ICS8430252-45 f emto c locks ? c rystal - to -3.3v lvpecl f requency s ynthesizer preliminary 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 4. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cc - 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.9v (v cco_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cc_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc _max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc _max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 4. lvpecl d river c ircuit and t ermination q1 v out v cc rl 50 v cc - 2v
8430252cg-45 www.icst.com/products/hiperclocks.html rev. b december 9, 2005 11 integrated circuit systems, inc. ICS8430252-45 f emto c locks ? c rystal - to -3.3v lvpecl f requency s ynthesizer preliminary r eliability i nformation t ransistor c ount the transistor count for ICS8430252-45 is: 2070 t able 8. ja vs . a ir f low t able for 16 l ead tssop ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 1 37.1c/w 118.2c/w 106.8c/w multi-layer pcb, jedec standard test boards 89. 0c/w 81.8c/w 78.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
8430252cg-45 www.icst.com/products/hiperclocks.html rev. b december 9, 2005 12 integrated circuit systems, inc. ICS8430252-45 f emto c locks ? c rystal - to -3.3v lvpecl f requency s ynthesizer preliminary p ackage o utline - g s uffix for 16 l ead tssop t able 9. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n6 1 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 9 . 40 1 . 5 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
8430252cg-45 www.icst.com/products/hiperclocks.html rev. b december 9, 2005 13 integrated circuit systems, inc. ICS8430252-45 f emto c locks ? c rystal - to -3.3v lvpecl f requency s ynthesizer preliminary t able 10. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom- mended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. i cs does not authorize or warrant any ics product for use in life support devices or critical medical instruments. the aforementioned trademarks, hiperclocks and femtoclocks are trademarks of integrated circuit systems, inc. or its subsidiari es in the united states and/or other countries. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 5 4 - g c 2 5 2 0 3 4 8 s c i5 4 c 2 5 2 0 3p o s s t d a e l 6 1e b u tc 0 7 o t c 0 t 5 4 - g c 2 5 2 0 3 4 8 s c i5 4 c 2 5 2 0 3p o s s t d a e l 6 1l e e r & e p a t 0 0 5 2c 0 7 o t c 0 f l 5 4 - g c 2 5 2 0 3 4 8 s c id b tp o s s t " e e r f - d a e l " d a e l 6 1e b u tc 0 7 o t c 0 t f l 5 4 - g c 2 5 2 0 3 4 8 s c id b tp o s s t " e e r f - d a e l " d a e l 6 1l e e r & e p a t 0 0 5 2c 0 7 o t c 0 . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n

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